1. Field of the Invention
The present invention relates to a composite semiconductor element obtained as a monolithic integrated circuit by forming a CCD (Charge Coupled Device) element, a CMOS element, and a bipolar element on a silicon semiconductor substrate and, more particularly, to a composite semiconductor element used for a TV or VTR.
2. Description of the Related Art
A composite integrated circuit element used for a TV or VTR is used as a monolithic integrated circuit obtained by forming a CCD delay line and a MOS transistor on a silicon semiconductor substrate. This CCD delay line serves to delay a signal and has an input/output circuit and a clock circuit respectively constituted by MOS transistors. With a recent tendency to reduce power consumption, these elements are constituted by CMOS elements so as to reduce the power source voltage from 9 V to 5 V. In addition, a circuit obtained by mounting a plurality of semiconductor elements in one package is currently available.
For example, a BiMOS element shown in FIG. 1 is designed such that the major surface of a p-type silicon semiconductor substrate is divided into a plurality of island regions A, B, and C by a selective oxide layer 2 for isolation, and a p-channel MOS transistor 3, an n-channel MOS transistor 4, and a CCD 5 are sequentially formed in the island regions A, B, and C, respectively to form a monolithic integrated circuit. The p-channel MOS transistor 3 is designed such that a so-called n-well region 6 is formed on the silicon semiconductor substrate 1, and an end portion of p-n junction formed by the n-well region 6 and substrate 1 is exposed on the upper surface of the silicon semiconductor substrate 1. This p-n junction end portion is protected by the selective oxide layer 2 for isolation to constitute a so-called planar structure. Since these structures are not different from known structures, a detailed description thereof will be omitted. Note that the MOS transistor includes a source region 7, a drain region 8, and a gate 9, and the CCD includes an extracting portion 10, thus constituting the BiMOS element.
In a conventional technique, a CCD element is formed on a silicon semiconductor substrate together with an n-channel (channel will be referred to as "ch" hereinafter) MOS transistor so as to constitute a monolithic integrated circuit. According to an arrangement of this circuit, a driving circuit, a clock driver, a sample/hold circuit, and an output circuit are generally arranged in addition to the CCD element. As described above, the power source voltage is changed from 9 V to 5 V for the following reason. With a recent tendency to form CMOS circuits so as to realize low power consumption, the power source voltage for, e.g., a bipolar element used together with such a CMOS circuit is required to be set to 5 V.
If, however, the power source voltage is set to 5 V, linearity of an operational amplifier used for the sample/hold circuit or the output circuit is degraded, and degradation of element characteristics is caused to decrease the yield. Furthermore, a delay line serves to only delay a signal, processing of this signal is performed by a circuit constituted by a bipolar element formed on another semiconductor substrate.